
Addressing
Appendix A
A13
Figure A.9
Illustration
of 1/3slot Addressing Using a 32point I/O Module
06
32-point
Input Module
1/2-slot
I/O Group
0
1/2-slot
I/O Group
0
1/2-slot
I/O Group
1
1/2-slot
I/O Group
1
Bit #
Bit #
01
03
05
07
11
13
15
17
01
03
05
07
11
13
15
17
00
02
04
06
10
12
14
16
00
02
04
10
12
14
16
17 10 7 0
Input W
ord 0
Image T
able
W
ords Allocated
for I/O Group 0
17 10 7 0
Outut W
ord 0
Unused
17 10 7 0
Input W
ord 1
Image T
able
W
ords Allocated
for I/O Group 1
17 10 7 0
Outut W
ord 1
Unused
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