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4.5 Using Interrupts in Application Tasks
The input module can be programmed to generate interrupts on the
basis of a time interval, an external latch input, an external count
stop input, a marker pulse and origin input, or a comparator equal
condition. Time intervalĆbased interrupts cannot be used with any
other interrupts.
Interrupts are used to synchronize software tasks to the occurrence
of a hardware event. This module provides the ability to synchronize
events beginning at 1.2 msec and increasing in increments of
500 msec depending on the priority level of the task receiving the
interrupt.
In order to use interrupts on the Pulsetach Input module, the module
must be in a rack containing a Processor module. Interrupts cannot
be used with Pulsetach Input modules located in remote racks.
You must first assign symbolic names to the interrupt control
registers on the module during configuration. Only one task may act
as the receiver for the interrupts generated by a Pulsetach Input
module. That task should declare the symbolic names assigned to
the interrupt control registers as COMMON. The Interrupt Status and
Control register (register 5) must be referenced in the hardware
EVENT statement in the task receiving the interrupt. The examples in
sections 4.4.1, 4.4.2, and 4.4.3 illustrate various uses of the interrupt
feature. Note that the receiving task uses either the SCAN_LOOP
(Control Block) statement or the WAIT ON (BASIC) statement to
actually receive the signal. (Refer to the Control Block and BASIC
Language instruction manuals.)
All interrupts are internally doubleĆbuffered. This helps to eliminate
spurious interrupts, which could cause system errors when the
module is operated in an electrically noisy environment. The
application task must provide a tightlyĆcoupled software handshake
with the external asynchronous interrupt inputs coming into the
module. Register 7, the Module Status register, is used in this
handshaking. The status bits in register 7 are set to one when an
interrupt input is received and remain set until the application
program clears them. As long as the status bits in the register are
equal to one, the module will not recognize additional interrupt
inputs as they occur.
4.6 Restrictions
This section describes limitations and restrictions on the use of the
Pulsetach Input module.
4.6.1 Writing Data to Registers
The module's counter registers (registers 0 and 1) are read only.
Attempts to write to them will cause a Bus Error (STOP ALL system
error indicated by a 31" on the faceplate of the Processor).
Some examples of programs that write to the module and must not
be used are:
D Referencing an input on the left side of an equal sign in a Control
Block or BASIC task.
D Referencing an input as an output in a Control Block function.
- 1
- 1
- Table of Contents 3
- 4
- 5
- 1.0 INTRODUCTION 7
- 8
- 2.0 MECHANICAL/ELECTRICAL 9
- DESCRIPTION 9
- 11
- 3.0 INSTALLATION 15
- 3.3 Module Replacement 18
- External PullĆUp Resistor 20
- 4.0 PROGRAMMING 23
- 4.1.2 Speed Detection Mode 24
- 4.1.3 External Latch Mode 24
- 25
- 4.2 Register Organization 26
- 4.3 Variable Configuration 36
- 4.4 Applying the Module 37
- 4.6 Restrictions 41
- 4.6.2 Use in Remote I/O Racks 42
- 5.0 DIAGNOSTICS AND 43
- TROUBLESHOOTING 43
- 5.2 Bus Error 46
- 5.3 Interrupt Problems 47
- 48
- 5.3.2 Hardware Event TimeĆout 49
- Appendix A 51
- 53
- Appendix C 55
- Appendix D 57
- Appendix E 59
- 60
- Appendix F 61
- Appendix G 67
- For additional information 70
- 1 Allen-Bradley Drive 70
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