Rockwell-automation T8110B/T8110 Trusted TMR Processor Instrukcja Użytkownika Pobierz pdf (Strona 20)

Trusted

TM

TMR Processor T8110B/T8110

Issue 18 Feb 08 PD-T8110B/T8110 20

RACK 7: (INFO)

11 INTEGER inputs

Channel 1

Chassis po

sition of AM

Channel 2 Slot position of AM

0 – Left

1 – Right

Channel 3 Indication of global health of AM

1 – No slice errors

0 – An error has been found

Channel 4

Current state of AM

Channel 5

Chassis position of SM

Channel 6 Slot position of SM

0 – Left

1 – Right

Channel 7 Indication of global health of SM

1 – No slice errors

0 – An error has been found

Channel 8

Current state of SM

Channel 9

Slice information of SM

–

see

Note

Channel 10

Reserved

Channel 11

Reserved

APPENDIX:

Note:

Bit 0 AM slice A:

1 - Slice is responding and there are no slice errors.

0 - Slice is either NOT responding or there is a slice error.

Bit 1 AM slice B:

1 - Slice is responding and there are no slice errors.

0 - Slice is either NOT responding or there is a slice error.

Bit 2 AM slice C:

1 - Slice is responding and there are no slice errors.

0 - Slice is either NOT responding or there is a slice error.

Bit 3 AM ejectors open:

1 - AM ejectors open.

0 - AM ejectors closed.

Bit 4 SM slice A:

1 - Slice is responding and there are no slice errors.

0 - Slice is either NOT responding or there is a slice error.

Bit 5 SM slice B:

1 - Slice is responding and there are no slice errors.

0 - Slice is either NOT responding or there is a slice error.

Bit 6 SM slice C:

1 - Slice is responding and there are no slice errors.

0 - Slice is either NOT responding or there is a slice error.

Bit 7 SM ejectors open:

1 - SM ejectors open.

0 - SM ejectors closed.

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